peb22504 Infineon Technologies Corporation, peb22504 Datasheet - Page 46

• Manufacturer Part Number: peb22504
• Description: Quad Line Interface Unit For E1dt1dj1 Quadliu
• Manufacturer: Infineon Technologies Corporation

In transmit direction, only the ternary or CMI interface is supported:
• Ternary signal
• CMI signal
4.2.2
Figure 14
The jitter attenuator can be placed in the receive or transmit path. If placed in the transmit
path, data is clocked into the JATT buffer with the transmit clock TCLK. If automatic
clock-switching is enabled (LIM5.ACS = 1), TCLK is replaced by the SYNC clock
automatically, if TCLK is missing. The active edge of TCLK (or SYNC, if TCLK is missing)
can be programmed by LIM4.TPE.
4.2.3
The integrated pulse-density enforcer can be activated (LIM0.PDE = 1) to ensure the
outgoing signal fulfills the pulse-density requirements of ANSI T1.403:
• No more than 15 consecutive zeros
• At least N ones in every time window of 8
Data Sheet
SCLKI
The received data stream on pins XDIP or XDIP/N is converted into a ternary signal
which is output on pins XL1 and XL2. In E1 mode the HDB3 and AMI line code is
employed. In T1 mode, B8ZS and AMI with or without zero code suppression is
supported (selected by LIM0.XC(1:0); the encoder can also be disabled).
The received data stream is converted into a CMI signal with HDB3 (E1) or B8ZS (T1/
J1) precoding.
MCLK
SYNC
values of 1 to 23.
RCLK
XL1
XL2
Transmit Clock System
Pulse-Density Enforcer
Transmit Clock System
Driver
DCO
Line
Shaper
Pulse
46
(N+1) digit time slots, with N taking on all
JATT
JATT
TCLK of 3 other
channels
SYNC
Interface Description
coder
En-
QuadLIU V1.1
PEB 22504
XDIP
XDIN
TCLK
2001-02
F0066