ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 30

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
2.2
2.2.1
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half
clkouta cycle before the multiplexed address/data bus (ad15–ad0 for the IA186EM or ao15–ao8
and ad7–ad0 for the IA188EM). The address bus is tristated during a bus hold or reset.
2.2.2
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The
address function of these pins can be disabled (see
function of these pins is enabled, the address will be present on this bus during t
and data will be present during t
If whb_n is not active, these pins are tristated during t
The address/data bus is tristated during a bus hold or reset.
These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h)
with configuration data during a power-on reset (POR).
2.2.3
These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or
memory and 8-bit data. The low-order address byte will be present on this bus during t
bus cycle and the 8-bit data will be present during t
The address function of these pins can be disabled (see
If wlb_n (IA186EM) is not active, these pins are tristated during t
The address/data bus is tristated during a bus hold or reset.
2.2.4
The address-only bus will contain valid high-order address bits during the bus cycle (t
t
These pins are combined with ad7–ad0 to complete the multiplexed address bus and are tristated
during a bus hold or reset condition.
4
) if the bus is enabled.
Pin Descriptions
a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous outputs with
tristate)
ad15–ad8 (IA186EM
with tristate)
ad7–ad0
ao15–ao8 (IA188EM)—Address-only bus (level-sensitive synchronous outputs
with tristate)
—
Address/Data bus (level-sensitive synchronous inouts with tristate)
®
)—
2
, t
Address/data bus (level-sensitive synchronous inouts
3
, and t
UNCONTROLLED WHEN PRINTED OR COPIED
4
of the same bus cycle.
Page 30 of 145
IA211050831-16
bhe_n/aden_n pin
2
, t
2
3
, t
, and t
bhe_n/aden_n pin
3
, and t
4
of the same bus cycle.
4
of the bus cycle.
2
, t
3
, and t
description). If the address
description).
4
of the bus cycle.
December 24, 2008
http://www.Innovasic.com
1
of the bus cycle
Customer Support:
1
Data Sheet
1-888-824-4184
, t
1
of the
2
, t
3
, and