ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 31

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
2.2.5
This signal indicates the presence of an address on the address bus (ad15–ad0 for the IA186EM
or ao15–ao8 and ad7–ad0 for the IA188EM), which is guaranteed to be valid on the falling edge
of ale.
2.2.6
This asynchronous signal provides an indication to the microcontroller that the addressed I/O
device or memory space will complete a data transfer. This active high signal is asynchronous
with respect to clkouta and if the falling edge of ardy is not synchronized to clkouta, an
additional clock cycle may be added
Signal ardy should be tied high to maintain a permanent assertion of the ready condition. On the
other hand, if the ardy signal is not used by the system it should be tied low, which passes
control to the srdy signal.
2.2.7
The bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower,
or both) are involved in the current memory access bus cycle as shown Table 9.
Table 9. Bus Cycle Types for bhe_n and ad0
The bhe_n does not require latching and during bus hold and reset is tristated. It is asserted
during t
The high- and low-byte write enable functions of bhe_n and ad0 are performed by whb_n and
wlb_n, respectively.
When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0 both being
high. During refresh cycles the a and ad busses may not have the same address during the
address phase of the ad bus cycle necessitating the use of ad0 as a determinant for the refresh
cycle rather than a0.
An additional signal is used for Pseudo-Static RAM (PSRAM) refreshes (see mcs3_n/rfsh_n pin
description).
There is a weak internal pull-up on bhe_n/aden_n obviating the need for an external pull-up and
reducing power consumption.
bhe_n
0
0
1
1
1
ale—Address Latch Enable (synchronous output)
ardy—Asynchronous Ready (level-sensitive asynchronous input)
bhe_n/aden_n (IA186EM)—Bus High Enable (synchronous output with
tristate)/Address Enable (input with internal pull-up)
and remains so through t
ad0
0
1
0
1
Type of Bus Cycle
Word Transfer
High-Byte Transfer (Bits [15–8])
Low-Byte Transfer (Bits [7–0])
Refresh
®
3
and t
UNCONTROLLED WHEN PRINTED OR COPIED
w
.
Page 31 of 145
IA211050831-16
December 24, 2008
http://www.Innovasic.com
Customer Support:
Data Sheet
1-888-824-4184