ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 70

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
5.1.17 LMCS (0a2h)
The Low-Memory Chip Select (LMCS) Register configures the LMCS provided to facilitate
access to the interrupt vector table located at 00000h or the bottom of memory. The lcs_n pin is
not active at reset.
The width of the data bus for the lcs_n space should be configured in the AUXCON register
before activating the lcs_n chip select pin, by any write access to the LMCS register. The value
of the LMCS register is undefined at reset except DA, which is set to 0 (see Table 33).
Table 33. Low-Memory Chip Select Register
Res
15
14
pcs3_n–pcs0_n Wait-State Encoding
Bit [2]—R2 → Ready Mode. When set to 1, external ready is ignored. When 0, it is
required. In each case the number of wait states is determined according to the
pcs3_n–pcs0_n Wait-State Encoding shown above.
Bits [1–0]—R1–R0 → Wait-State Value (see pcs3_n–pcs0_n Wait-State Encoding
above). The pcs6_n–pcs5_n and pcs3_n–pcs0_n pins are multiplexed with the PIO pins.
For these to function as chip selects, the PIO mode and direction settings for these pins
must be set to 0 for normal operation.
Bit [15]—Reserved → Set to 0.
Bits [14–12]—UB2–UB0 → Upper Boundary. These bits define the upper boundary of
memory accessed by the lcs_n chip select. The list below presents the possible block-size
configurations (a 512-Kbyte maximum).
UB2–UB0
R3
0
0
0
0
1
1
1
1
13
R1
0
0
1
1
0
0
1
1
12
R0
0
1
0
1
0
1
0
1
®
11
Reserved
Wait States
10
15
0
1
2
3
5
7
9
9
8
DA
UNCONTROLLED WHEN PRINTED OR COPIED
7
PSE
6
Page 70 of 145
IA211050831-16
Reserved
5
4
3
R2
2
R1–R0
1
0
December 24, 2008
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