ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 63

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Bit [14]—DDEC → Destination Decrement. When set to 1, it automatically decrements
the destination address after each transfer. The address is decremented by 1 or 2,
depending on the byte/word bit (Bn/W, Bit [0]). The address does not change if the
increment and decrement bits are set to the same value (00b or 11b).
Bit [13]—DINC → Destination Increment. When set to 1, it automatically increments
the destination address after each transfer. The address is incremented by 1 or 2,
depending on the byte/word bit (Bn/W, Bit [0]). The address does not change if the
increment and decrement bits are set to the same value (00b or 11b).
Bit [12]—SM/IOn → Source Address Space Select selects memory or I/O space for the
source address. When set to 1, the source address is in memory space. When 0, it is in
I/O space.
Bit [11]—SDEC → Source Decrement. When set to 1, it automatically decrements the
destination address after each transfer. The address is decremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [10]—SINC → Source Increment. When set to 1, it automatically increments the
destination address after each transfer. The address is incremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [9]—TC → Terminal Count. The DMA decrements the transfer count for each DMA
transfer. When set to 1, the source or destination synchronized DMA transfers terminate
when the count reaches 0. When 0, they do not. Unsynchronized DMA transfers always
end when the count reaches 0, regardless of this bit’s setting.
Bit [8]—INT → Interrupt. When this bit is set to 1, the DMA channel generates an
interrupt request on completion of the transfer count. However, for an interrupt to be
generated, the TC bit must also be set to 1.
Bits [7–6]—SYN1–SYN0 → Synchronization Type bits each select channel
synchronization types as shown below. The value of these bits is ignored if TDRQ
(Bit [4]) is set to 1. A processor reset causes these bits to be set to 11b.
Synchronization Bit Channel Selection
SYN1
0
0
1
1
SYN0
0
1
0
1
®
Unsynchronized
Source Synchronized
Destination Synchronized
Reserved
Sync Type
UNCONTROLLED WHEN PRINTED OR COPIED
Page 63 of 145
IA211050831-16
December 24, 2008
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