ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 98

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Table 79. Synchronous Serial Status Registers
5.2
Additional information on the operation and programming of the IA186EM/ IA188EM can be
found in the following Advanced Micro Devices (AMD) publications:
6.
Table 80
and
presents the read cycle.
cycle timing.
Table 84
Figure 15
Figure 16
Figure 17
timing.
15
82
14
present the alphabetic and numeric keys to waveform parameters, respectively.
Bits [15–3]—Reserved.
Bit [2]—RE/TE Receive/Transmit Error Detect → This bit is set to 1 when a read of the
Synchronous Serial Received register or a write to one of the transmit register is detected
while the interface is busy (PB = 1). This bit is reset to 0 when the SDEN output is not
active (DE1–DE0 in the SSC register are 00h).
Bit [1]—DR/DT Data Receive/Transmit Complete → This bit is set to a 1 when the
transmission of data Bit [7] is completed (SCLK rising edge) during a transmit or receive
operation. This bit is reset by a read of the SSR register, when either the SSD0 or SSD1
register is written, when the SSS register is read (unless the SSI completes an operation
and sets the bit in the same cycle), or when both SDEN0 and SDEN1 become inactive.
Bit [0]—PB SSI Port Busy → This bit indicates that a data transmit or receive is
occurring when it is set to 1. When set to 0, it indicates that the port is ready to transmit
or receive data.
Reference Documents
Am186 EM and Am188 EM Microcontrollers User’s Manual, February 1997,
Publication 19713.
Am186 EM/EMLV and Am188 EM/EMLV Preliminary Data Sheet, February 1997,
Publication 19168, Rev. E, Amendment 0.
AC Specifications
Figure 18
presents the AC characteristics over commercial operating ranges (40 MHz).
presents the write cycle timing.
13
presents the PSRAM read cycle.
presents the PSRAM write cycle.
presents the PSRAM refresh cycle.
Figure 13
12
presents the interrupt acknowledge cycle.
11
®
Reserved
10
Figure 12
presents the write cycle.
9
8
presents the multiple read cycles.
7
UNCONTROLLED WHEN PRINTED OR COPIED
6
5
Table 85
Table 86
4
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Table 87
IA211050831-16
3
Figure 14
presents the PSRAM read cycle timing.
RE/TE
presents the PSRAM write cycle timing.
presents the PSRAM refresh cycle
2
presents the multiple write cycles.
Table 88
DR/DT
1
Table 83
presents the interrupt
PB
0
December 24, 2008
presents the read
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Tables 81
Figure 11