ia186em Innovasic Semiconductor Inc., ia186em Datasheet - Page 60

• Manufacturer Part Number: ia186em
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Table 19. Processor Release Level Register
5.1.4
The Power-save CONtrol Register controls several miscellaneous system I/O and timing
functions. The PDCON contains 0000h at reset (see Table 20).
Table 20. Power-Save Control Register
15
PSEN
15
14
Note: The value of PSEN is not restored upon execution of an IRET
instruction.
Bits [15–8]—PRL7–PRL0 → The latest Processor Release Level.
Bits [7–0]—Reserved.
Bit [15]—PSEN → When set to 1, enables the power-save mode causing the internal
operating clock to be divided by the value in F2–F0. External interrupts or interrupts
from internal interrupts automatically clear PSEN. Software interrupts and exception do
not clear PSEN.
Bits [14–12]—Reserved → These bits read back as 0.
Bit [11]—CBF → When set to 1, the clkoutb output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [10]—CBD → When set to 1, the clkoutb output is pulled low. When 0, it is driven
as an output per the CBF bit.
Bit [9]—CAF → When set to 1, the clkouta output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
PDCON (0f0h)
PRL Value
14
13
Reserved
PRL7–PRL0
01h
02h
03h
04h
13
12
12
11
®
Release Level
Processor
CBF
11
10
C
D
E
F
9
CBD
10
8
7
CAF
UNCONTROLLED WHEN PRINTED OR COPIED
9
6
CAD
5
8
Reserved
Page 60 of 145
IA211050831-16
4
7
3
Reserved
6
2
5
1
4
0
3
F2
2
F1
1
F0
0
December 24, 2008
http://www.Innovasic.com
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