h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 153

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h8s-2646

Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
6.1
The PC break controller (PBC) provides functions that simplify program debugging. Using these
functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with
the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:
instruction fetch, data read, data write, and data read/write.
6.1.1
The PC break controller has the following features:
• Two break channels (A and B)
• The following can be set as break compare conditions:
• The timing of PC break exception handling after the occurrence of a break condition is as
• Module stop mode can be set
 24 address bits
 Bus cycle
 Bus master
follows:
 Immediately before execution of the instruction fetched at the set address (instruction
 Immediately after execution of the instruction that accesses data at the set address (data
 The initial setting is for PBC operation to be halted. Register access is enabled by clearing
Bit masking possible
Instruction fetch
Data access: data read, data write, data read/write
Either CPU or CPU/DTC can be selected
fetch)
access)
module stop mode.
Overview
Features
Section 6 PC Break Controller (PBC)
Rev. 5.00 Sep 22, 2005 page 127 of 1136
Section 6 PC Break Controller (PBC)
REJ09B0257-0500

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