h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 706

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 20 ROM
20.4
The registers used to control the on-chip flash memory when enabled are shown in table 20.3.
Table 20.3 Register Configuration
Notes: 1. Lower 16 bits of the address.
20.5
20.5.1
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when
FWE = 1, then setting the PV or EV bit. Program mode for addresses H'00000 to H'1FFFF is
entered by setting SWE bit to 1 when FWE = 1, then setting the PSU bit, and finally setting the P
bit. Erase mode for addresses H'00000 to H'1FFFF is entered by setting SWE bit to 1 when FWE
= 1, then setting the ESU bit, and finally setting the E bit. FLMCR1 is initialized by a reset, and in
hardware standby mode and software standby mode. Its initial value is H'80 when a high level is
Rev. 5.00 Sep 22, 2005 page 680 of 1136
REJ09B0257-0500
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register FLPWCR *
Initial value:
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
4. FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.
Register Configuration
Register Descriptions
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is not set, these registers are initialized to H'00.
Use byte access on these registers.
R/W:
Bit:
FWE
— *
R
7
SWE
R/W
6
0
Abbreviation
FLMCR1 *
FLMCR2 *
EBR1 *
EBR2 *
RAMER *
ESU
R/W
5
0
4
4
4
4
4
4
PSU
R/W
4
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
EV
3
0
Initial Value
H'00 *
H'00
H'00 *
H'00 *
H'00
H'00 *
R/W
PV
2
3
3
3
2
0
R/W
E
1
0
Address *
H'FFA8
H'FFA9
H'FFAA
H'FFAB
H'FEDB
H'FFAC
R/W
P
0
0
1