h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 81

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Size refers to the operand size.
2.6.4
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the
operation to be carried out on the operand. The operation field always includes the first four bits of
the instruction. Some instructions have two operation fields.
(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
(4) Condition Field: Specifies the branching condition of Bcc instructions.
Type
Block data
transfer
instruction
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Basic Instruction Formats
B: Byte
W: Word
L: Longword
Instruction
EEPMOV.B
EEPMOV.W
Size *
—
—
1
Function
if R4L ≠ 0 then
else next;
if R4 ≠ 0 then
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
Repeat @ER5+ → @ER6+
Until R4L = 0
Repeat @ER5+ → @ER6+
Until R4 = 0
R4L–1 → R4L
R4–1 → R4
Rev. 5.00 Sep 22, 2005 page 55 of 1136
REJ09B0257-0500
Section 2 CPU