h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 758
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h8s-2646
Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2646.pdf
(1165 pages)
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Section 21 Clock Pulse Generator
21.1.2
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 21.1 shows the register
configuration.
Table 21.1 Clock Pulse Generator Register
Note:* Lower 16 bits of the address.
21.2
21.2.1
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control, selection of operation when the PLL circuit frequency multiplication factor is
changed, and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Rev. 5.00 Sep 22, 2005 page 732 of 1136
REJ09B0257-0500
Name
System clock control register
Low-power control register
Bit 7
PSTOP
0
1
Bit
Initial value
R/W
High Speed Mode,
Medium Speed Mode,
Subactive Mode
φ output (initial value)
Fixed high
Register Configuration
Register Descriptions
System Clock Control Register (SCKCR)
:
:
:
PSTOP
R/W
7
0
—
—
6
0
Sleep Mode,
Subsleep Mode
φ output
Fixed high
SCKCR
Abbreviation
LPWRCR
—
—
5
0
Description
—
—
4
0
R/W
R/W
R/W
Software Standby
Mode, Watch Mode,
and Direct Transition
Fixed high
Fixed high
STCS
R/W
3
0
Initial Value
H'00
H'00
SCK2
R/W
2
0
SCK1
R/W
High impedance
High impedance
Hardware
Standby Mode
1
0
Address *
H'FDE6
H'FDEC
SCK0
R/W
0
0
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