h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 927

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

IRR—Interrupt Register
Overload Frame Interrupt Flag
Bit
Initial value
Read/Write
Note: * Only 1 can be written, to clear the flag.
0
1
[Clearing condition]
Writing 1
Overload frame transmission
[Setting conditions]
When overload frame is transmitted
Bus Off Interrupt Flag
0
1
[Clearing condition]
Writing 1
Bus off state caused by transmit error
[Setting condition]
When TEC
R/(W) *
IRR7
15
0
256
R/(W) *
IRR6
14
Receive Overload Warning Interrupt Flag
0
0
1
[Clearing condition]
Writing 1
Error warning state caused by receive error
[Setting condition]
When REC
R/(W) *
Transmit Overload Warning Interrupt Flag
0
1
IRR5
13
0
[Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC
96
Error Passive Interrupt Flag
0
1
Remote Frame Request Interrupt Flag
0
1
[Clearing condition]
Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
When TEC
[Clearing condition]
Clearing of all bits in RFPR (remote request wait register) in the mailbox,
which enables the receive interrupt requests in MBIMR
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed, when corresponding MBIMR = 0
R/(W) *
IRR4
96
12
0
Receive Message Interrupt Flag
0
1
[Clearing condition]
Clearing of all bits in RXPR (receive complete register) in the mailbox,
which enables the receive interrupt requests in MBIMR
Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed, when
corresponding MBIMR = 0
128 or REC
Note: After canceling a reset or returning from hardware standby
Reset Interrupt Flag
0
1
Rev. 5.00 Sep 22, 2005 page 901 of 1136
R/(W) *
H'F812
[Clearing condition]
Writing 1
Transition to hardware reset (HCAN module stop, software
standby)
[Setting condition]
When reset processing is completed after hardware reset
transition (HCAN module stop, software standby)
IRR3
mode, the module stop bit is initialized yo 1. HCAN then
enters a module-stopped state.
11
0
128
Appendix B Internal I/O Register
R/(W) *
IRR2
10
0
R/(W) *
IRR1
9
0
REJ09B0257-0500
R/(W) *
IRR0
8
1
HCAN