MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 101

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Mirror Function
Table 41: 32 Meg x 18 Ball Assignments with MF Ball Tied HIGH
RESET Operation
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
M
A
D
G
H
K
N
B
C
E
F
L
J
V
V
V
V
A13
A10
V
V
V
V
A9
NF
DDQ
1
EXT
EXT
DD
DD
SS
SS
SS
V
V
A18
TCK
CS#
V
V
V
V
A5
NF
NF
NF
2
SSQ
SSQ
DD
SS
SS
SS
V
V
The mirror function ball (MF) is a DC input used to create mirrored ballouts for simple
dual-loaded clamshell mounting. If the MF ball is tied LOW, the address and command
balls are in their true layout. If the MF ball is tied HIGH, the address and command balls
are mirrored around the central y-axis (column 7). The following table shows the ball
assignments when the MF ball is tied HIGH for a x18 device. Compare that table to Ta-
ble 1 (page 12) to see how the address and command balls are mirrored. The same balls
are mirrored on the x36 device.
V
V
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW. There are no restrictions for when it can go LOW. After RESET# goes LOW, it must
remain LOW for 100ns. During this time, the outputs are disabled, ODT (R
(High-Z), and the DRAM resets itself. Prior to RESET# going HIGH, at least 100 stable CK
cycles with NOP commands must be given to the RLDRAM. After RESET# goes HIGH,
the DRAM must be reinitialized as though a normal power-up was executed. All refresh
counters on the DRAM are reset, and data stored in the DRAM is assumed unknown af-
ter RESET# has gone LOW.
A12
V
V
V
A8
NF
NF
NF
NF
DDQ
DDQ
SSQ
SSQ
3
DD
DD
DD
V
V
V
V
TDO
A17
V
NF
NF
NF
A4
NF
NF
DDQ
DDQ
SSQ
SSQ
4
SS
V
V
V
V
V
V
BA0
V
NF
NF
A3
NF
NF
DDQ
DDQ
DDQ
DDQ
SSQ
SSQ
5
DD
V
V
REF#
V
BA2
V
V
NF
NF
NF
NF
NF
NF
DDQ
DDQ
6
SSQ
SSQ
SS
101
DK0#
DK1#
DM0
DM1
V
DK0
DK1
V
CK#
MF
V
ZQ
CK
7
REF
REF
SS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DQ12
DQ17
QK0#
QK1#
V
V
DQ7
DQ2
WE#
V
V
BA3
V
DDQ
DDQ
8
SSQ
SSQ
SS
DQ15
V
V
V
V
DQ5
V
QK0
QK1
V
BA1
V
A1
DDQ
DDQ
DDQ
DDQ
576Mb: x18, x36 RLDRAM 3
SSQ
SSQ
9
DD
DQ13
V
V
DQ8
V
DQ3
DQ1
DQ9
V
A16
TDI
V
10
A2
DDQ
DDQ
SSQ
SSQ
SS
© 2011 Micron Technology, Inc. All rights reserved.
DQ10
DQ16
V
V
DQ6
DQ0
V
V
V
V
A14
V
11
A6
Mirror Function
DDQ
DDQ
SSQ
SSQ
DD
DD
DD
QVLD
DQ14
DQ4
V
V
TMS
TT
A15
NC
V
V
V
V
A0
12
SSQ
SSQ
DD
SS
SS
SS
) turns off
1
RESET#
DQ11
V
V
V
A11
A19
V
V
V
V
V
A7
13
DDQ
EXT
EXT
DD
DD
SS
SS
SS