MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 47

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
24. Single-ended signal parameter.
25. For x36 device this specification references the skew between the falling edge of QK0
26. The DRAM output timing is aligned to the nominal or average clock. The following out-
27. The
28.
29. These parameters are measured from the input data strobe signal (DK/DK#) crossing to
30. These parameters are measured from a command/address signal transition edge to its
31. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
32. If
33. This specification is defined as any bank command (READ, WRITE, AREF) to a multi-bank
and QK1 to QVLD0 and the falling edge of QK2 and QK3 to QVLD1.
put parameters must be derated by the actual jitter error when input clock jitter is
present, even when within specification. This results in each parameter becoming larger.
The following parameters are required to be derated by subtracting
t
subtracting
t
slew rate and 2 V/ns CK, CK# differential slew rate.
its respective clock signal crossing (CK/CK#). The specification values are not affected by
the amount of clock jitter applied as they are relative to the clock signal crossing. These
parameters should be met whether or not clock jitter is present.
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether or not clock jitter is present.
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
issued to the same address. Whatever data was previously written to the address will be
output with the READ command.
command or a multi-bank command to any bank command. This specification only ap-
plies to quad bank WRITE, 3-bank AREF and 4-bank AREF commands. Dual bank WRITE,
2-bank AREF, and all single bank access commands are not bound by this specification.
CKQK (MIN), and
IS(base) and
t
WTR is violated, the data just written will not be read out when a READ command is
t
DQSCKdll_dis parameter begins RL - 1 cycles after the READ command.
t
ERR(10per),min:
t
IH(base) values are for a single-ended 1 V/ns control/command/address
t
LZ (MIN). The following parameters are required to be derated by
47
t
CKQK (MAX),
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
HZ (MAX), and
AC Electrical Characteristics
576Mb: x18, x36 RLDRAM 3
t
LZ (MAX).
© 2011 Micron Technology, Inc. All rights reserved.
t
ERR(10per),max: