MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 70

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

AUTO REFRESH Protocol
Burst Length (BL)
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
The AUTO REFRESH (AREF) protocol is selected with bit MR1[8]. There are two ways in
which AREF commands can be issued to the RLDRAM. Depending upon how bit
MR1[8] is programmed, the memory controller can issue either bank address-control-
led or multibank AREF commands. Bank address-controlled AREF uses the BA[3:0] in-
puts to refresh a single bank per command. Multibank AREF is enabled by setting bit
MR1[8] HIGH during an MRS command. This refresh protocol enables the simultane-
ous refreshing of a row in up to four banks. In this method, the address pins A[15:0] rep-
resent banks 0–15, respectively. More information on both AREF protocols can be found
in AUTO REFRESH Command (page 77).
Burst length is defined by MR1[9] and MR1[10]. Read and write accesses to the
RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Figure 34 (page 71) shows the different burst lengths with respect to a READ com-
mand. Changes in the burst length affect the width of the address bus (see the following
table for details).
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
Table 39: Address Widths of Different Burst Lengths
Burst Length
2
4
8
70
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A[19:0]
A[18:0]
A[17:0]
x18
576Mb: x18, x36 RLDRAM 3
Configuration
Mode Register 1 (MR1)
© 2011 Micron Technology, Inc. All rights reserved.
A[18:0]
A[17:0]
x36
NA