MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 72

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Mode Register 2 (MR2)
Figure 35: MR2 Definition for Non-Multiplexed Address Mode
READ Training Register (RTR)
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
M19
0
0
1
1
M18
0
1
0
1
Note:
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
The READ training register (RTR) is controlled through MR2[2:0]. It is used to output a
predefined bit sequence on the output balls to aid in system timing calibration. MR2[2]
is the master bit that enables or disables access to the READ training register, and
MR2[1:0] determine which predefined pattern for system calibration is selected. If
MR2[2] is set to 0, the RTR is disabled, and the DRAM operates in normal mode. When
MR2[2] is set to 1, the DRAM no longer outputs normal read data, but a predefined pat-
tern that is defined by MR2[1:0].
Prior to enabling the RTR, all banks must be in the idle state (
enabled, all subsequent READ commands will output four bits of a predefined se-
quence from the RTR on all DQs. The READ latency during RTR is defined with the Data
Latency bits in MR0. To loop on the predefined pattern when the RTR is enabled, suc-
cessive READ commands must be issued and satisfy
considered "Don't Care" during RTR READ commands. Bank address bits BA[3:0] must
access Bank 0 with each RTR READ command.
RTR READ commands to Bank 0. When the RTR is enabled, only READ commands are
allowed. When the last RTR READ burst has completed and
MRS command can be issued to exit the RTR. Standard RLDRAM 3 operation may then
start after
bled.
If MR2[1:0] is set to 00 a 0-1-0-1 pattern will be output on all DQs with each RTR READ
command. If MR2[1:0] is set to 01, a 0-1-0-1 pattern will output on all even DQs and the
opposite pattern, a 1-0-1-0, will output on all odd DQs with each RTR READ command.
Note: Enabling RTR may corrupt previously written data.
Reserved
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
the MRS command.
t
MRSC has been met. The RESET function is supported when the RTR is ena-
21
BA3
0
1
M4
0
0
1
1
20
0
BA2
1
M3
0
1
0
1
19
BA1
MRS
18
BA0
WRITE Protocol
Reserved
Single Bank
Quad Bank
Dual Bank
A17
Reserved
17-5
...
72
WRITE
4
A4
3
A3
En
2
A2
RTR
M2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
A1
0
1
M1
0
0
1
1
0
A0
READ Training Register Enable
Normal RLDRAM Operation
M0
READ Training Enabled
0
1
0
1
Address Bus
Mode Register (Mx)
t
RC does not need to be met in between
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
576Mb: x18, x36 RLDRAM 3
READ Training Register
t
RTRS. Address balls A[19:0] are
0-1-0-1 on all DQs
Mode Register 2 (MR2)
Reserved
Reserved
t
RTRE has been satisfied, an
t
RC met). When the RTR is
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