MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 97

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Data Latency in Multiplexed Address Mode
REFRESH Command in Multiplexed Address Mode
Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing
Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Command
Command
Address
Address
Bank
CK#
CK
Bank
CK#
CK
Bank n
T0
AC
Ax
1
AREF
T0
Ax
1
NOP
T1
Ay
Notes:
Note:
When in multiplexed address mode, data latency (READ and WRITE) begins when the
Ay part of the address is issued with any READ or WRITE command.
from the clock edge in which the command and Ax part of the address is issued in both
multiplexed and non-multiplexed address mode.
Similar to other commands when in multiplexed address mode, both modes of AREF
(single and multibank) are executed on the rising clock edge, following the one on
which the command is issued. However, when in bank address-controlled AREF, as only
the bank address is required, the next command can be applied on the following clock.
When using multibank AREF, the bank addresses are mapped across Ax and Ay so a sub-
sequent command cannot be issued until two clock cycles later.
Bank 0
NOP
AREF
T2
T1
Ay
1. Any command subject to
1. Usage of multibank AREF subject to
2. Any command subject to
Bank 1
AREF
T3
AREF
T2
Ax
1
Bank 2
AREF
T4
NOP
T3
Bank 3
Ay
T5
AREF
t
t
97
RC specification.
RC specification.
Bank 4
AREF
T6
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
AREF
SAW and
T4
Ax
1
Bank 5
T7
AREF
t
MMD specifications.
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
T5
NOP
Ay
Bank 6
T8
AREF
© 2011 Micron Technology, Inc. All rights reserved.
Bank 7
T9
AREF
Bank n
T6
AC
Ax
t
2
RC is measured
T10
Bank n
AC
Ax
1
Don’t Care
T7
NOP
Ay
Don’t Care
T11
Ay