MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 94

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Figure 59: MR0 Definition for Multiplexed Address Mode
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
0
21
1
BA3
Notes:
0
Reserved
20
1
BA2
19
MRS
BA1
18
BA0
Ax
Ay A18.......A10
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
2. BL8 not allowed.
3. BL4 not allowed.
A18.......A10
Reserved
the MRS command.
17-10
M9
0
1
M8
AM
0
1
A9
Non-multiplexed
9
Address MUX
DLL
Multiplexed
8
A8
DLL Enable
Disable
Enable
Data Latency
A9
7
6
A8
A5
5
M7
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A4 A3
94
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
3
t
M5
RC_MRS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
A4
M4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A3
1
Data Latency (RL & WL)
A0
0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RL = 10 ; WL = 11
RL = 11 ; WL = 12
RL = 12 ; WL = 13
RL = 13 ; WL = 14
RL = 14 ; WL = 15
RL = 15 ; WL = 16
RL = 16 ; WL = 17
RL = 9 ; WL = 10
RL = 3 ; WL = 4
RL = 4 ; WL = 5
RL = 5 ; WL = 6
RL = 6 ; WL = 7
RL = 7 ; WL = 8
RL = 8 ; WL = 9
Reserved
Reserved
Mode Register (Mx)
Address Bus
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
M3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
© 2011 Micron Technology, Inc. All rights reserved.
M0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
Reserved
Reserved
Reserved
Reserved
Reserved
RC_MRS
2
10
11
12
3
4
2,3
5
6
7
8
9
2
2