MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 14

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Table 3: Ball Descriptions
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
QKx, QKx#
DKx, DKx#
WE#, REF#
DQ[35:0]
TMS, TDI
Symbol
DM[1:0]
BA[3:0]
CK/CK#
A[19:0]
RESET#
QVLDx
TCK
CS#
MF
ZQ
Output Output data clocks: QK and QK# are opposite-polarity output data clocks. They are free-run-
Output Data valid: The QVLD ball indicates that valid output data will be available on the subsequent
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
Description
Address inputs: A[19:0] define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings along with BA[3:0].
They are sampled at the rising edge of CK.
Bank address inputs: Select the internal bank to which a command is being applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations contin-
ue.
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is refer-
enced to both edges of QK. During WRITE commands, the data is sampled at both edges of DK.
Input data clock: DKx and DKx# are differential input data clocks. All input data is referenced
to both edges of DKx. For the x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0 and
DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1 and DK1#. For the x18 device, DQ[8:0]
are referenced to DK0 and DK0#, and DQ[17:9] are referenced to DK1 and DK1#. DKx and DKx#
are free-running signals and must always be supplied to the device.
Input data mask: DM is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM0 is used to mask the lower byte for the x18 device and DQ[8:0] and
DQ[26:18] for the x36 device. DM1 is used to mask the upper byte for the x18 device and
DQ[17:9] and DQ[35:27] for the x36 device. Tie DM[1:0] to V
IEEE 1149.1 clock input: This ball must be tied to V
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# (together with CS#) de-
fine the command to be executed.
Reset: RESET# is an active LOW CMOS input referenced to V
are asynchronous. RESET# is a CMOS input defined with DC HIGH ≥ 0.8 x V
V
External impedance: This signal is used to tune the device’s output impedance and ODT. RZQ
needs to be 240Ω, where RZQ is a resistor from this signal to ground.
ning signals and during READ commands are edge-aligned with the DQs. For the x36 device,
QK0, QK0# align with DQ[8:0]; QK1, QK1# align with DQ[17:9]; QK2, QK2# align with DQ[26:18];
QK3, QK3# align with DQ[35:27]. For the x18 device, QK0, QK0# align with DQ[8:0]; QK1, QK1#
align with DQ[17:9].
rising clock edge. There is a single QVLD ball for the x18 device and two, QVLD0 and QVLD1, for
the x36 device. QVLD0 aligns with DQ[17:0]; QVLD1 aligns with DQ[35:18].
Mirror function: The mirror function ball is a DC input used to create mirrored ballouts for sim-
ple dual-loaded clamshell mounting. If the ball is tied to V
in their true layout. If the ball is tied to V
tied HIGH or LOW and cannot be left floating. MF is a CMOS input defined with DC HIGH ≥ 0.8 x
V
DDQ
DD
and DC LOW ≤ 0.2 x V
.
DDQ
.
14
DDQ
, they are in the complement location. MF must be
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
SS
if the JTAG function is not used.
576Mb: x18, x36 RLDRAM 3
SS
SS
, the address and command balls are
SS
if not used.
. RESET# assertion and deassertion
© 2011 Micron Technology, Inc. All rights reserved.
DD
and DC LOW ≤ 0.2 x