MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 79

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MT44K16M36

Manufacturer Part Number
MT44K16M36
Description
576Mb: x18, x36 RLDRAM 3
Manufacturer
MICRON [Micron Technology]
Datasheet

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INITIALIZATION Operation
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
The RLDRAM 3 device must be powered up and initialized in a predefined manner. Op-
erational procedures other than those specified may result in undefined operations or
permanent damage to the device.
The following sequence is used for power-up:
10. The RLDRAM 3 is ready for normal operation.
1. Apply power (V
2. Ensure that RESET# is below 0.2 × V
3. After the power is stable, RESET# must be LOW for at least 200µs to begin the initi-
4. After 100 or more stable input clock cycles with NOP commands, bring RESET#
5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP
6. Load desired settings into MR0.
7.
8. After the DLL is reset and Long ZQ Calibration is enabled, the input clock must be
9. Load desired settings into MR2. If using the RTR, follow the procedure outlined in
V
all ramp to their respective minimum DC levels within 200ms.
remain disabled (High-Z) and ODT is off (R
will remain High-Z until MR0 command. All other inputs may be undefined dur-
ing the power ramp.
alization process.
HIGH.
commands for 10,000 cycles.
t
ing DLL Reset and Long ZQ Calibration.
stable for 512 clock cycles while NOPs are issued.
the READ Training Function – Back-to-Back Readout figure prior to entering nor-
mal operation.
MRSC after loading the MR0 settings, load operating parameters in MR1, includ-
DDQ
. V
DD
must not exceed V
EXT
, V
DD
, V
79
DDQ
EXT
). Apply V
during power supply ramp. V
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DDQ
DD
during power ramp to ensure the outputs
and V
TT
576Mb: x18, x36 RLDRAM 3
is also High-Z). DQs, and QK signals
INITIALIZATION Operation
EXT
before, or at the same time as,
© 2011 Micron Technology, Inc. All rights reserved.
EXT
, V
DD
, V
DDQ
must

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