MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 96

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Figure 61: MR2 Definition for Multiplexed Address Mode
Table 40: Address Mapping in Multiplexed Address Mode
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Width
Data
x36
x18
Length
Burst
2
4
2
4
8
M19
0
0
1
1
M18
0
1
0
1
Ball
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Note:
Note:
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
A0
A0
A0
A0
A0
A0
X
X
X
X
X
Reserved
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
1. X = “Don’t Care”
the MRS command.
M4
0
0
1
1
A3
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
M3
21
0
1
0
1
0
BA3
1
20
0
BA2
1
WRITE Protocol
19
A4
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
BA1
MRS
Single Bank
Quad Bank
Dual Bank
Reserved
18
BA0
Ax
Ay A18.......A5
Reserved
A18.......A5
A5
A5
A5
A5
A5
A5
17-5
X
X
X
X
X
96
WRITE
4
A4 A3
A8
M2
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
0
1
3
En
READ Training Register Enable
2
Normal RLDRAM Operation
Address
A4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
READ Training Enabled
RTR
A9
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
1
A3
M1
0
0
1
1
0
A0
M0
0
1
0
1
Mode Register (Mx)
A10
A10
A10
A10
A19
A10
A10
X
X
X
X
576Mb: x18, x36 RLDRAM 3
Even DQs: 0-1-0-1 ; Odd DQs: 1-0-1-0
Multiplexed Address Mode
Address Bus
READ Training Register
A13
0-1-0-1 on all DQs
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
Reserved
Reserved
© 2011 Micron Technology, Inc. All rights reserved.
A14
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A18
A15
A15
A18
A15
A18
A15
A15
X
X