MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 62

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Commands
Table 36: Command Descriptions
Table 37: Command Table
Note 1 applies to the entire table
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Command
NOP
MRS
READ
WRITE
AREF
Operation
NOP
MRS
READ
WRITE
AUTO REFRESH
Description
The NOP command prevents new commands from being executed by the DRAM.
Operations already in progress are not affected by NOP commands. Output values depend on com-
mand history.
Mode registers MR0, MR1, and MR2 are used to define various modes of programmable operations of
the DRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initi-
alization and retains the stored information until it is reprogrammed, RESET# goes LOW, or until the
device loses power. The MRS command can be issued only when all banks are idle, and no bursts are
in progress.
The READ command is used to initiate a burst read access to a bank. The BA[3:0] inputs select a bank,
and the address provided on inputs A[19:0] select a specific location within a bank.
The WRITE command is used to initiate a burst write access to a bank (or banks). MRS bits MR2[4:3]
select single, dual, or quad bank WRITE protocol. The BA[x:0] inputs select the bank(s) (x = 3, 2, or 1
for single, dual, or quad bank WRITE, respectively). The address provided on inputs A[19:0] select a
specific location within the bank. Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is registered
LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the cor-
responding data inputs will be ignored (that is, this part of the data word will not be written).
The AREF command is used during normal operation of the RLDRAM 3 to refresh the memory con-
tent of a bank. There are two methods by which the RLDRAM 3 can be refreshed, both of which are
selected within the mode register. The first method, bank address-controlled AREF, is identical to the
method used in RLDRAM2. The second method, multibank AREF, enables refreshing of up to four
banks simultaneously. More info is available in the Auto Refresh section. For both methods, the com-
mand is nonpersistent, so it must be issued each time a refresh is required.
Notes:
The following table provides descriptions of the valid commands of the RLDRAM 3 de-
vice. All command and address inputs must meet setup and hold times with respect to
the rising edge of CK.
WRITE
Code
READ
AREF
NOP
MRS
1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank ad-
2. Address width varies with burst length and configuration; see the Address Widths of
3. Bank address signals (BA) are used only during bank address-controlled AREF; Address
dress; OPCODE = mode register bits
Different Burst Lengths table for more information.
signals (A) are used only during multibank AREF.
CS#
H
L
L
L
L
WE#
62
X
H
H
L
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
REF#
H
H
X
L
L
576Mb: x18, x36 RLDRAM 3
OPCODE
A[19:0]
A
A
A
X
© 2011 Micron Technology, Inc. All rights reserved.
OPCODE
BA[3:0]
BA
BA
BA
X
Commands
Notes
2
2
3