MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 66

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
When in multiplexed address mode, only 11 address balls are required to control the
RLDRAM, as opposed to 20 address balls when in non-multiplexed address mode. The
data bus efficiency in continuous burst mode is only affected when using the BL = 2 set-
ting because the device requires two clocks to read and write data. During multiplexed
mode, the bank addresses as well as WRITE and READ commands are issued during the
first address part, Ax. The Address Mapping in Multiplexed Address Mode table shows
the addresses needed for both the first and second rising clock edges (Ax and Ay, re-
spectively).
After MR0[9] is set HIGH, READ, WRITE, and MRS commands follow the format descri-
bed in the Command Description in Multiplexed Address Mode figure. Refer to Multi-
plexed Address Mode for further information on operation with multiplexed address-
ing.
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
576Mb: x18, x36 RLDRAM 3
Mode Register 0 (MR0)
© 2011 Micron Technology, Inc. All rights reserved.