MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 46

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
10. Spread spectrum is not included in the jitter specification values. However, the input
11. The clock’s
12. The period jitter,
13.
14.
15. The cycle-to-cyle jitter,
16. The cumulative jitter error,
17.
18. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
19. The setup and hold times are listed converting the base specification values (to which
20. Pulse width of an input signal is defined as the width between the first crossing of
21. Bits MR0[3:0] select the number of clock cycles required to satisfy the minimum
22.
23. When the device is operated with input clock jitter, this parameter needs to be derated
5. All timings that use time-based values (ns, µs, ms) should use
6. The term “strobe” refers to the DK and DK# or QK and QK# differential crossing point
7. The output load defined in Figure 18 (page 39) is used for all AC timing and slew rates.
8. When operating in DLL disable mode, Micron does not warrant compliance with normal
9. The clock’s
correct number of clocks. In the case of noninteger results, all minimum limits should be
rounded up to the nearest whole integer, and all maximum limits should be rounded
down to the nearest whole integer.
when DK and QK, respectively, is the rising edge. Clock, or CK, refers to the CK and CK#
differential crossing point when CK is the rising edge.
The actual test load may be different. The output signal voltage reference point is
V
mode timings or functionality.
t
clock jitter. Input clock jitter is allowed provided it does not exceed values specified and
must be of a random Gaussian distribution in nature.
clock can accommodate spread spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of
trum may not use a clock rate below
utive clocks and is the smallest clock half-period allowed, with the exception of a devia-
tion due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
age or nominal clock. It is allowed in either the positive or negative direction.
t
ing edge to the following falling edge.
t
ing edge to the following rising edge.
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
50, is the amount of clock time allowed to accumulate consecutively away from the
average clock over n number of clock cycles.
t
ferential DK, DK# slew rate.
tion edge to its respective data strobe signal (DK, DK#) crossing.
derating tables apply) to V
of 1 V/ns, are for reference only.
V
ue. Minimum
whole number to determine the earliest clock edge that the subsequent command can
be issued to the bank.
t
t
by the actual
put deratings are relative to the SDRAM input clock).
CK(avg),min is the smallest clock rate allowed, with the exception of a deviation due to
CH(abs) is the absolute instantaneous clock high pulse width as measured from one ris-
CL(abs) is the absolute instantaneous clock low pulse width as measured from one fall-
DS(base) and
QKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and DQ[8:0].
QKQ13 defines the skew between QK1 and DQ[35:27] and between QK3 and DQ[17:9].
DDQ
REF(DC)
/2 for single-ended signals and the crossing point for differential signals.
and the consecutive crossing of V
t
t
CK(avg) is the average clock over any 200 consecutive clocks and
CH(avg) and
t
t
t
JIT(per) (the larger of
RC value must be divided by the clock period and rounded up to the next
DH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns dif-
t
JIT(per), is the maximum deviation in the clock period from the aver-
t
CK(avg) as a long-term jitter component; however, the spread spec-
t
JIT(cc), is the amount the clock period can deviate from one cycle
t
CL(avg) are the average half-clock period over any 200 consec-
46
REF
t
ERR(nper), where n is the number of clocks between 2 and
when the slew rate is 1 V/ns. These values, with a slew rate
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
JIT(per),min or
t
CK(avg),min.
REF(DC)
.
AC Electrical Characteristics
576Mb: x18, x36 RLDRAM 3
t
JIT(per),max of the input clock; out-
© 2011 Micron Technology, Inc. All rights reserved.
t
CK(avg) to determine the
t
RC val-