AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 23

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

Register
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
HBLK Mode 1 Operation
Multiple repeats of the HBLK signal are enabled by setting
HBLKMODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 27).
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. HBLK line alternation can be used in conjunction with
V-pattern odd/even alternation or on its own. Separate toggle
positions are available for even and odd lines. If even/odd line
alternation is not required, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Increasing H-Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse
widths to be increased during the HBLK interval. As shown in
Figure 28, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable
this feature, the HCLK_WIDTH register (Address 0x34,
H1/H3
H2/H4
HBLK
HBLKSTART
Length
3b
3b
3b
3b
3b
HBLKTOGE1
HBLKREP NUMBER 1
Range
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS
HBLKREP = 3
HBLKTOGE2
HBLKLEN
HBLKTOGE3
Figure 27. HBLK Repeating Pattern Using HBLKMODE = 1
HBLKTOGE4
HBLKREP NUMBER 2
Description
HBLK Mode 2, Odd Field Repeat Area 1 pattern.
HBLK Mode 2, Odd Field Repeat Area 2 pattern.
HBLK Mode 2, Odd Field Repeat Area 3 pattern.
HBLK Mode 2, Odd Field Repeat Area 4 pattern.
HBLK Mode 2, Odd Field Repeat Area 5 pattern.
Rev. C | Page 23 of 92
Bits [7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled. The reduced
frequency occurs only for H1 to H8 pulses that are located
within the HBLK area.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support
wide HCLKs.
Table 12. HCLK Width Register
Register
HCLK_WIDTH
HBLKREP NUMBER 3
Length
4b
Description
Controls H1 to H8 pulse widths
during HBLK as a fraction of pixel rate
0: Same frequency as pixel rate
1: 1/2 pixel frequency, that is, doubles
the HCLK pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
…
15: 1/30 pixel frequency
HBLKEND
AD9992