AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 66

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Vertical Toggle Position Placement Near Counter Reset
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. Before
the internal counters are reset, there is a region of 36 pixels
during which no toggle positions should be programmed.
As shown in Figure 78 for master mode, the last 36 pixels before
the HD falling edge must not be used for toggle position placement
of the V, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
(PIXEL COUNTER)
PIXEL NO.
NOTES:
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHPLOC (INTERNAL SAMPLING EDGE).
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE, AT SHDLOC (INTERNAL SAMPLING EDGE).
3. DEPENDING ON THE VALUE OF SHPLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 32, SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
H-COUNTER
CLPOB
EDGE SHOULD NOT OCCUR WITHIN 1 CYCLE IMMEDIATELY BEFORE VD FALLING EDGE.
INTERNAL
INTERNAL
INTERNAL
SHPLOC
SHDLOC
HD
H1
CLI
CLO
VD
HD
HD
0
1
2
3
4
HBLKTOG1
HBLKTOG2
CLPOB_TOG1
CLPOB_TOG2
X
X
X
t
VDHD
t
HDCLI
X
t
HDCLO
X X
MASTER MODE
Figure 77. Example of Slave Mode Register Setting to Obtain Desired Toggle Positions
Figure 76. External VD/HD and Internal H-Counter Synchronization, Slave Mode
60
100
103
112
X
X
X
X
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
SLAVE MODE
X
X
X
X X X
Rev. C | Page 66 of 92
X
X
35.5 CYCLES
X
60
X X
1
Figure 79 shows the same example for slave mode. The same
restriction applies: the last 36 pixels before the counters are
reset cannot be used. However, in slave mode, the counter reset
is delayed with respect to VD/HD placement, so the inhibited
area is different than it is in master mode.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
X
X
X
X
X X X
100
2
3
103
X
X
X
112
X
4
X
X
X
X
X
H-COUNTER
RESET
0
1 2
t
CLIDLY