AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 60

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AD9992_07

Manufacturer Part Number
AD9992_07
Description
12-Bit CCD Signal Processor with Precision Timing Generator
Manufacturer
AD [Analog Devices]
Datasheet
AD9992
XV1 TO XV24
DESIGNATOR
SYNC
SCP
VD
HD
SYNC
VD
FIELD
SYNC
VD
1
5
1
NOTES
1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL.
VD REGISTERS ARE UPDATED HERE.
1
1
7
1
2
3
SYNC_MASK_VD IS A NEW REGISTER. HI WILL MASK VD. DEFAULT = HI.
SYNC_MASK_HD IS A NEW REGISTER. HI WILL MASK HD. DEFAULT = LO.
V-OUTPUT PULSES CONTINUE IN SEQUENCE.
Figure 70. Special SYNC Mode Effect on Field Designator
1
1
1
2
3
FIELD DESIGNATOR IS INCREMENTED ON BOTH SYNC EDGES.
Figure 69. Register Update Behavior
Figure 68. Enhanced SYNC Mode 3
Rev. C | Page 60 of 92
VDLEN
3
1
1
1
5
1
7

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