AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 30

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the CLPOB, PBLK, and HBLK Pattern Registers)
Register
HOLD
VMASK_EN
CONCAT_GRP
VREP_MODE
LASTREPLEN_EN
LASTTOG_EN
HDLENE
HDLENO
VPOL_A
VPOL_B
VPOL_C
VPOL_D
GROUPSEL_0
GROUPSEL_1
VPATSELA
VPATSELB
VPATSELC
VPATSELD
VSTARTA
VSTARTB
VSTARTC
VSTARTD
VLENA
VLENB
VLENC
VLEND
VREPA_1
VREPA_2
Length
4b
4b
4b
2b
4b
4b
13b
13b
24b
24b
24b
24b
24b
24b
5b
5b
5b
5b
13b
13b
13b
13b
13b
13b
13b
13b
13b
13b
Selects line alternation for V-output repetitions. Note separate controls for Group A and Groups B/C/D.
HD line length for even lines in the V-sequence.
HD line length for odd lines in the V-sequence.
Group A start polarity bits for each XV1 to XV24 output.
Group D start polarity bits for each XV1 to XV24 output.
Selected V-pattern for Group A.
Selected V-pattern for Group B.
Selected V-pattern for Group C.
Selected V-pattern for Group D.
Start position for the selected V-Pattern Group A.
Start position for the selected V-Pattern Group B.
Start position for the selected V-Pattern Group C.
Start position for the selected V-Pattern Group D.
Length of selected V-Pattern Group A.
Length of selected V-Pattern Group B.
Length of selected V-Pattern Group C.
Length of selected V-Pattern Group D.
Number of repetitions for the V-Pattern Group A for first lines (even).
Description
Use in conjunction with VMASK_EN.
1: HOLD function instead of FREEZE/RESUME function.
Enables the masking of XV1 to XV24 outputs at the locations specified by the FREEZE/RESUME registers.
1: Enable masking for all groups. One bit for each set of Freeze and Resume Positions 1 to 4.
Combines toggle positions of Groups A/B/C/D when enabled. Only Group A settings for start, polarity, length,
and repetition are used when this mode is selected.
0: Disable.
1: Enable the addition of all toggle positions from VPATSELA/B/C/D.
2: Test mode only. Do not use.
…
15: Test mode only. Do not use.
0: Disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP _EVEN for all lines.
1: 2-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.
2: 3-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN, VREP_ODD,
3: 4-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation.
Enables a separate pattern length to be used during the last repetition of the V-sequence. One bit for
each group (A, B, C, and D). Set bit high to enable. Group A is the LSB. Recommended value is enabled.
Enables a final toggle position to be added at the end of the V-sequence. The toggle position is shared
by all V-outputs in the same group. One bit for each group. Set bit high to enable. Group A is the LSB.
Group B start polarity bits for each XV1 to XV24 output.
Group C start polarity bits for each XV1 to XV24 output.
Assigns each XV1 to XV12 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV1, Bits
[3:2] are for XV2 … Bits [23:22] are for XV12.
0: Assign to Group A
1: Assign to Group B
2: Assign to Group C
3: Assign to Group D
Assigns each XV13 to XV24 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV13,
Bits [3:2] are for XV14 … Bits [23:22] are for XV24.
0: Assign to Group A.
1: Assign to Group B.
2: Assign to Group C.
3: Assign to Group D.
Number of repetitions for the V-Pattern Group A for second lines (odd).
VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.
Rev. C | Page 30 of 92