AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 28

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns for
each XV1 to XV24 output signal. Table 13 summarizes the registers
available for generating each of the V-pattern groups. The first,
second, third, and fourth toggle positions (XVTOG1, XVTOG2,
XVTOG3, and XVTOG4) are the pixel locations within the line
where the pulse transitions. All toggle positions are 13-bit values,
allowing their placement anywhere in the horizontal line.
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the V-pattern
group within the line; VLEN designates the total length of
the V-pattern group, which determines the number of pixels
between each of the pattern repetitions when repetitions are used.
Table 13. Vertical Pattern Group Registers
Register
XVTOG1
XVTOG2
XVTOG3
XVTOG4
XV24
XV1
XV2
PROGRAMMABLE SETTINGS:
1
2
3
4
HD
START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
FIRST TOGGLE POSITION.
SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
Length
13b
13b
13b
13b
Description
First toggle position within line for each XV1 to XV24 output, relative to VSTART value.
Second toggle position, relative to VSTART value
Third toggle position, relative to VSTART value
Fourth toggle position, relative to VSTART value
1
1
1
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
2
2
2
4
Figure 34. Vertical Pattern Group Programmability
3
3
3
Rev. C | Page 28 of 92
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART value
plus the toggle position.
When the selected V-output is designated as a VSG pulse, either
the XVTOG1/XVTOG2 or XVTOG3/XVTOG4 pair is selected
using V-Sequence Address 0x02, VSGPATSEL. All four toggle
positions are not simultaneously available for VSG pulses.
Unused V-channels must have their toggle positions programmed
to either 0 or maximum value. This prevents unpredictable
behavior because the default values of the V-pattern group registers
are unknown.