AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 64

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
POWER-UP SEQUENCE FOR MASTER MODE
When the AD9992 is powered up, the following sequence is
recommended (refer to Figure 74 for each step). A SYNC signal
is required for master mode operation. If an external SYNC
pulse is not available, it is possible to generate an internal SYNC
event by writing to the SWSYNC register.
1.
2.
3.
4.
5.
6.
XV1 TO XV24
Turn on the power supplies for AD9992 and start the master
clock, CLI.
Reset the internal AD9992 registers by writing 1 to the
SW_RST register (Address 0x10).
By default, Vertical Output XV1 to Vertical Output XV24
are low. If necessary, write to the Standby3 output polarity
(Address 0x26) to set different polarities for the vertical
outputs in order to avoid damage to the V-driver and
CCD. Write to Address 0x1C to configure each V-output
as a vertical transfer clock (XV) or sensor pulse (VSG).
If using an external V-driver in conjunction with the
AD9992, power up the V-driver supplies, VH and VL,
anytime after Step 3 is complete to set the proper polarities.
Load the required registers to configure the necessary
vertical timing, horizontal timing, high speed timing, and
shutter timing. Set the recommended start-up address,
0xD8, to 0x888.
To place the part into normal power operation, write 0x04
to Register Address 0x00. This sets the STANDBY register
(AFE Register Address 0x00, Bits [1:0]) to normal operation
H-CLOCKS
SUPPLIES
(OUTPUT)
(OUTPUT)
WRITES
POWER
(INPUT)
SERIAL
(INPUT)
SUBCK
SYNC
CLI
VD
HD
0V
HI-Z BY
DEFAULT
HI-Z BY
DEFAULT
LOW BY
DEFAULT
HI-Z BY
DEFAULT
2
3
Figure 74. Recommended Power-Up Sequence and Synchronization, Master Mode
4
5
VH SUPPLY FOR V-DRIVER (IF USING EXTERNAL V-DRIVER)
VL SUPPLY FOR V-DRIVER (IF USING EXTERNAL V-DRIVER)
Rev. C | Page 64 of 92
6
H2, H4, H6, H8
H1, H3, H5, H7, RG
7
7.
8.
9.
10.
8
and enables the OB clamp (AFE Register Address 0x00,
Bit 2). If the CLO output is being used to drive a crystal, also
power up the CLO oscillator by writing 1 to Address 0x15.
By default, the internal timing core is held in a reset state,
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x14) to start the internal
timing core operation. Note that, if a 2× clock is used for
the CLI input, the CLIDIVIDE register (0x0D) should be
set to 1 before resetting the timing core.
Configure the AD9992 for master mode timing by writing 1
to the MASTER register (Address 0x20).
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge. Normally OUTCONTROL takes effect
after the next VD edge; however, because the part is just
being powered up, there is no VD edge until the rising
edge of the SYNC signal.
Generate a SYNC event. If SYNC is high at power-up,
bring the SYNC input low for a minimum of 100 ns, and
then bring SYNC high again. This causes the internal
counters to reset and starts VD/HD operation. The first
VD/HD edge allows VD-updated register updates to
occur, including OUTCONTROL to enable all outputs.
If a hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit 14) can be used to initiate a SYNC event.
t
9
SYNC
10
1H
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE
FIRST FIELD
1V