AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 24

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AD9992_07

Manufacturer Part Number
AD9992_07
Description
12-Bit CCD Signal Processor with Precision Timing Generator
Manufacturer
AD [Analog Devices]
Datasheet
AD9992
HBLK
HD
H2
H1
HD
H2
H1
HBLKSTART
HBLKSTART
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS
HBLK
H1/H3
H2/H4
RA0H2REPA RA0H2REPB
REPEAT AREA 0
RA0H1REPA RA0H1REPB
A
HBLKSTARTA
B
REPEAT AREA 0
C
HBLKSTARTB
REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3
1/F
PIX
Figure 28. Generating Wide H-Clock Pulses During HBLK Interval
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER
HBLKLEN
RA0H2REPC
RA0H1REPC
HBLKSTARTC
TO CREATE TWO REPEAT AREAS
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RA*H*REP* = 0
Figure 29. HBLK Mode 2 Operation
Figure 30. HBLK Mode 2 Registers
HBLKREP = 2
ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
Rev. C | Page 24 of 92
2 × (1/F
RA1H2REPA RA1H2REPB
RA1H1REPA RA1H1REPB
PIX
)
REPEAT AREA 1
REPEAT AREA 4 REPEAT AREA 5
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RA*H*REP* REGISTERS
RA1H2REPC
RA1H1REPC
HBLKEND
HBLKEND

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