AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 76

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
Address
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1F
Table 31. VD/HD Registers
Address
0x20
0x21
0x22
Data
Bits
[2]
[3]
[4]
[5]
[6]
[7]
[12:8]
[13]
[14]
[0]
[0]
[27:0]
[12:0]
[13]
[14]
[15]
[16]
[17]
[27:0]
[27:0]
[27:0]
[27:0]
[23:0]
[23:0]
[24]
[0]
[1]
Data
Bits
[0]
[0]
[12:0]
[25:13]
Default
Value
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
FF0000
0
0
1
1
Default
Value
0
0
0
0
Update
Type
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
Update
Type
SCK
VD
VD
Mnemonic
SYNCSUSPEND
ENH_SYNC_EN
SYNC_MASK_HD
SYNC_MASK_VD
SYNC_MASK_V
SHADOW_EN
TEST
UPDATE_SHADOW
SWSYNC
TGCORE_RSTB
OSC_RSTB
TEST
UPDATE
PREVENTUP
SYNC_RST_SHUTEN
REG_RST_SHUT
GPO_RST_SYNC
GPO_LINE_COUNT_OFFSET
TEST
TEST
TEST
TEST
VSGSELECT
VSGMASK_CTL
VSGMASK_CTL_EN
HCNT14_EN
PBLK_MASK_EN
Mnemonic
MASTER
VDHDPOL
HDRISE
VDRISE
Rev. C | Page 76 of 92
Description
VD/HD master or slave mode:
0: Slave mode.
1: Master mode.
VD/HD active polarity:
0: Low.
1: High.
Rising edge location for HD. Minimum value is 36 pixels.
Rising edge location for VD.
Each bit selects XV pulses for use as VSG pulses.
Description
Suspend clocks during SYNC active pulse:
0: Do not suspend.
1: Suspend.
1: Enable enhanced sync/shutter operations.
1: Mask HD during SYNCSUSPEND.
1: Mask VD during SYNCSUSPEND.
1: Mask XV outputs during SYNCSUSPEND.
1: Enable use of shadow registers.
Test mode only. Must be set to 0.
1: Writes to shadow bits affect shadow registers, not
primary.
1: Initiate software SYNC event (self-clears to 0 after SYNC).
Timing core reset bar. 0: reset TG core;
1: resume operation.
CLO oscillator reset bar:
0: Oscillator in power-down state.
1: Resume oscillator operation.
Test mode only. Must be set to 0.
Serial update line.
Sets the line (HD) within the field to update the VD-updated
registers.
Prevents the update of the VD-updated registers:
0: Normal update.
1: Prevent update of VD-updated registers.
1: Enable reset of the shutter control after SYNC operation
occurs.
1: Forces shutter control to reset.
1: Reset shutter and GPO control at SYNC operation.
0: First line in a field is considered Line 1 for GPOs.
1: First line in a field is considered Line 0 for GPOs.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0xA.
VSG masking. Overrides settings in field registers when
enabled.
0: Disable VSGMAK_CTL bits. VSG masking is controlled by
1: Enable VSGMASK_CTL bits to control VSG masking.
1: Enable 14-bit H-counter.
1: Disable clamp operation if PBLK is active at the same time
field registers.
as CLPOB.