AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 77
AD9992_07
Manufacturer Part Number
AD9992_07
Description
12-Bit CCD Signal Processor with Precision Timing Generator
Manufacturer
AD [Analog Devices]
Datasheet
1.AD9992_07.pdf
(92 pages)
- Current page: 77 of 92
- Download datasheet (2Mb)
Table 32. I/O and Charge Pump Registers
Address
0x23
0x24
0x25
0x26
0x27
Data
Bits
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[9:7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[24:0]
[24:0]
[7:0]
[15:8]
0
0
Default
Value
0
0
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
0
0
0
1
0
0
0
Update
Type
SCK
SCK
SCK
SCK
SCK
Mnemonic
OSC_NVR
XV_NVR
IO_NVR
DATA_NVR
TEST
TEST
LDO_32_EN
HCLKMODE
SEL_VCO
SEL_DIV
SEL_CLI
O31V
O32V
O33V
O34V
TEST
TEST
TEST
TEST
TEST
TEST
TEST
CP_PDN
VT_STBY12
VT_STBY3
GP_STDBY12
GP_STDBY3
Rev. C | Page 77 of 92
Description
Oscillator normal voltage range. Set to match CLIVDD supply voltage.
0: 1.8 V.
1: 3.3 V.
XV output normal voltage range. Set to match XVVDD supply voltage.
0: 1.8 V.
1: 3.3 V.
I/O normal voltage range. Set the match IOVDD supply voltage.
0: 1.8 V.
1: 3.3 V.
Data pin normal voltage range. Set to match DRVDD supply voltage.
0: 1.8 V I/O.
1: 3.3 V I/O.
Test mode only. Set to 0.
Test mode only. Set to 0.
1: Internal regulator enable for 3.2 V output.
Selects HCLK output configuration. Should be written to desired value.
001: Mode 1.
010: Mode 2.
100: Mode 3.
All other values are invalid.
1: Internal CP clock select VCO.
1: Internal CP clock select divided-down version of CLI (default).
1: Internal CP clock select CLI.
1: CP output voltage is 3.1 V.
1: CP output voltage is 3.2 V.
1: CP output voltage is 3.3 V.
1: CP output voltage is 3.4 V.
Test mode only. Use default values only.
Test mode only. Use default values only.
Test mode only. Use default values only.
Test mode only. Use default values only.
Test mode only. Use default values only.
Test mode only. Use default values only.
Test mode only. Use default values only.
Charge pump power-down.
1: Power-down.
0: CP is running.
[23:0] Standby1 and Standby2 polarity for XV [23:0].
[24] Standby1 and Standby2 polarity for XSUBCK.
Settings also apply when OUTCONTROL = low.
[23:0] Standby3 polarity for XV [23:0].
[24] Standby3 polarity for XSUBCK.
Standby1 and Standby2 polarity for GPO [7:0].
Settings also apply when OUTCONTROL = low.
Standby3 polarity for GPO [7:0].
AD9992
Related parts for AD9992_07
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
DPG2 EVAL ADAPTER FOR XILINX BOARDS
Manufacturer:
Analog Devices Inc
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
Xilinx FMC Interface
Manufacturer:
Analog Devices Inc
Datasheet:
Part Number:
Description:
RF Development Tools Sransceiver board for FMC evaluation kit
Manufacturer:
Analog Devices
Part Number:
Description:
Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table
Manufacturer:
AD [Analog Devices]
Datasheet:
Part Number:
Description:
Analog Devices: Data Converters: DAC 8-Bit, 10 ns to 100 ns Converters Selection Table
Manufacturer:
AD [Analog Devices]
Datasheet:
Part Number:
Description:
Low-Power Analog Front End with DSP Microcomputer
Manufacturer:
AD [Analog Devices]
Datasheet:
Part Number:
Description:
2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
Manufacturer:
AD [Analog Devices]
Datasheet: