AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 74

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

AD9992
UPDATING NEW REGISTER VALUES
The AD9992 internal registers are updated at different times,
depending on the particular register. Table 28 summarizes the four
register update types: SCK, VD, SG-Line, and SCP. Tables in the
Complete Register Listing section also contain an Update Type
column that identifies when each register is updated.
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Table 28. Register Update Locations
Update Type
SCK
VD
SG-Line
SCP
SCK Updated—As soon as the 28th data bit (D27) is clocked
in, some registers are immediately updated. These registers
are used for functions that do not require gating with the next
VD boundary, such as power-up and reset functions.
VD Updated—More registers are updated at the next VD
falling edge. By updating these values at the next VD edge,
the current field is not corrupted and the new register
values are applied to the next field. The VD update can be
further delayed past the VD falling edge by using the
UPDATE register (Address 0x17). This delays the VD-
updated register updates to any HD line in the field. Note
that the field registers are not affected by the UPDATE
register.
SG-Line Updated—A few of the shutter registers are updated
at the HD falling edge at the start of the SG active line.
XV1 TO XV24
SERIAL
WRITE
VSG
VD
HD
Description
When the 28th data bit (D27) is clocked in, the register is immediately updated.
Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at
Address 0x17. FIELD registers are not affected by the UPDATE register.
Register is updated at the HD falling edge at the start of the SG-active line.
Register is updated at the next SCP when the register is used.
UPDATED
SCK
Figure 87. Register Update Locations (See Table 28 for Definitions)
SCP0
USE VSEQ2
UPDATED
REGION 0
VD
SCP1
UPDATED
SGLINE
USE VSEQ3
REGION 1
SG
Rev. C | Page 74 of 92
SCP2
UPDATED
SCP
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Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge
where a sequence change position (SCP) occurs. See Figure 78
and Figure 79 for examples of what this inhibit area looks like in
master and slave modes. This restriction applies to the V-pattern,
V-sequence, and field registers. As shown in Figure 87, writing
to these registers before the VD falling edge typically avoids
loading these registers during SCP locations.
USE VSEQ5
REGION 2
These registers control the SUBCK signal so that the SUBCK
output is not updated until the SG line occurs.
SCP Updated—At the next SCP where they are used,
the V-pattern group and V-sequence registers are updated.
For example, in Figure 87 this field has selected Region 1 to
use VSEQ3 for the vertical outputs. This means that a write
to any of the VSEQ3 registers, or any of the V-pattern
group registers, which are referenced by VSEQ3, updates at
SCP1. If multiple writes are made to the same register, the last
one done before SCP1 is the one that is updated. Likewise,
register writes to any VSEQ5 registers are updated at SCP2;
register writes to any VSEQ8 registers are updated at SCP3.
SCP3
USE VSEQ8
REGION 3
SCP0