AD9992_07 AD [Analog Devices], AD9992_07 Datasheet - Page 39

• Manufacturer Part Number: AD9992_07
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: AD [Analog Devices]

Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions,
and within each region, a different V-sequence can be selected.
Figure 48 shows how the sequence change positions (SCP)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the field
registers. Table 17 summarizes the registers used to create the
fields.
The SEQ registers, one for each region, select which V-sequences
are active in each region. The MULT_SWEEP registers, one for
each region, are used to enable sweep mode and/or multiplier
mode in any region. The SCP registers create the line boundaries
for each region. The VDLEN register specifies the total number of
lines in the field. The HDLEN register specifies the total number of
Table 17. Field Registers (CLPOB, PBLK Masking Shown in Table 10)
Register
SEQx
MULT_SWEEP
SCP
VDLEN
HDLASTLEN
VSGPATSEL
SGMASK
SGACTLINE1
SGACTLINE2
Length
5b
2b
13b
13b
13b
24b
24b
13b
13b
Range
0 to 31 V-sequence number
0 to 3
0 to 8191 line number
0 to 8191 lines
0 to 8191 pixels
High/low
High/low, each VSG
0 to 8191 line number
0 to 8191 line number
Description
Selected V-sequence for each region in the field.
Enables multiplier mode and/or sweep mode for each region.
Total number of lines in each field.
Length in pixels of the last HD line in each field.
VSGPATSEL selects which V-pattern toggle positions are used. When set to 0,
Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
Sequence change position for each region.
Set high to mask each individual VSG output.
0: Multiplier off, sweep off.
1: Multiplier off, sweep on.
2: Multiplier on, sweep off.
3: Multiplier on, sweep on.
[0]: XV1 selection (0 = use XVTOG1, XVTOG2; 1 = use XVTOG3, XVTOG4).
…
[23]: XV24 selection.
[0]: XV1 mask.
…
[23]: XV24 mask.
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pixels per line, and the HDLASTLEN register specifies the
number of pixels in the last line of the field.
The VPATSECOND register is used to add a second V-pattern
group to the XV1 to XV10 outputs in the vertical sensor gate
(VSG) line. The SGMASK register is used to enable or disable each
individual VSG output. There are two bits for each VSG output
to enable separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low enables
the output. The VSGPATSEL register assigns one of the eight
SG patterns to each VSG output. Individual SG patterns are created
separately using the SG pattern registers. The SGACTLINE1
register specifies which line in the field contains the VSG outputs.
The optional SGACTLINE2 register allows the same VSG pulses to
be repeated on a different line. Separate masking is not available
for SGACTLINE1 and SGACTLINE2.
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