PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 12

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
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Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Clock Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Clock Mode 4 (High Speed) Configuration . . . . . . . . . . . . . . . . . . . . 145
Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . 150
Clock Mode 5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
DPLL Algorithm for NRZ and NRZI
Coding with Phase Shift Enabled (CCR0:PSD = ‘0’) . . . . . . . . . . . . . 156
DPLL Algorithm for NRZ and NRZI
Encoding with Phase Shift Disabled (CCR0:PSD = ‘1’). . . . . . . . . . . 156
DPLL Algorithm for FM0, FM1 and Manchester Coding . . . . . . . . . . 157
Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 162
NRZ and NRZI Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
SCC Receive Data Flow (HDLC Modes) part a) . . . . . . . . . . . . . . . . 173
SCC Receive Data Flow (HDLC Modes) part b) . . . . . . . . . . . . . . . . 174
SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . 175
Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Flow Control: Reception of S-Commands and Protocol Errors . . . . . 181
No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 184
Data Transmission (without error), Data Transmission (with error) . . 184
PPP Mapping/Unmapping Example . . . . . . . . . . . . . . . . . . . . . . . . . 189
Asynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Out-of-Band DTE-DTE Bi-directional Flow Control . . . . . . . . . . . . . . 196
Out-of-Band DTE-DCE Bi-directional Flow Control . . . . . . . . . . . . . . 197
BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Transmit Descriptor List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Receive Descriptor List Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
ASYNC/BISYNC Receive Status Character Format . . . . . . . . . . . . . 386
DSCC4 Logical Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Interrupt Vector Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Selecting one time-slot of programmable delay and width . . . . . . . . 148
Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 178
Transmission/Reception of I-Frames and Flow Control. . . . . . . . . . . 181
Overview of Data Stuctures in shared Memory before Transmission 214
Overview of Data Stuctures in shared Memory after Transmission. . 219
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Data Sheet 09.98
PEB 20534