PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 162

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
• Timing mode 2 (CCR0:SC1, SC0 = ‘11’)
7.7.5
In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC
bits) to be active when data (frame or character) is being transmitted. This signal is
delayed by one clock period with respect to the data output TxD, and marks all data bits
that could be transmitted without collision (see figure 55). In this way a configuration
may be implemented in which the bus access is resolved on a local basis (collision bus)
and where the data are sent one clock period later on a separate transmission line.
Figure 55
Note: For details on the functions of the RTS pin refer to “Modem Control Signals
7.8
The SCC supports the following coding schemes for serial data:
– Non-Return-To-Zero (NRZ)
– Non-Return-To-Zero-Inverted (NRZI)
– FM0 (also known as Bi-Phase Space)
– FM1 (also known as Bi-Phase Mark)
– Manchester (also known as Bi-Phase)
7.8.1
NRZ: The signal level corresponds to the value of the data bit. By programming bit DIV
(CCR1 register), the SCC may invert the transmission and reception of data.
NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the
beginning of the bit cell.
Data is output with the falling clock edge and evaluated with the next falling clock
edge. Thus one complete clock period is available between data output and collision
detection.
(RTS, CTS, CD)” on page 164.
Functions Of Signal RTS in HDLC Mode
Data Encoding
NRZ and NRZI Encoding
Request-to-Send in Bus Operation
CxD
TxD
RTS
Serial Communication Controller (SCC) Cores
162
Collision
ITT00242
Data Sheet 09.98
PEB 20534