PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 424

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Table 121
No. Parameter
30
31
32
33
34
35
36
37
38
39
40
61
41
42
62
1)
Note: T
If extended LALE timing is selected via bit ’EALE’ in register LCONF
LALE to LCLKO delay
LALE pulse width
Address phase width
LA, LBHE hold to LCLKO delay
LCSO active to LCLKO delay
LRD, LWR active/inactive to LCLKO delay
LRD pulse width
LCSO inactive to LCLKO delay
LD to LCLKO setup time
LD to LCLKO hold time
LRD, LWR active to cycle start delay
cycle end to next cycle start delay
LWR pulse width
LD to LCLKO hold delay
LD to LWR inactive delay
LD tristate delay to LCLKO
cycle end to next cycle start delay
MCTC is the number of master clock wait states (in LBI clock cycles) selected in
register LCONF.
T
LRDY control signal if enabled via bit ’RDEN’ in register LCONF.
T
LBICLK
LRDY
PCICLK
is the number of additional wait states (in LBI clock cycles) introduced by
is the LBI clock time period which depends on the LBI clock division factor.
is the PCI clock time period.
LBI Timing (synchronous, multiplexed bus)
424
5
5
5
1 T
min.
5
5
0
25
+ 5
2T
2T
2 T
5 T
LBICLK
LBICLK
PCICLK
Electrical Characteristics
(1.25 T
LBICLK
LBICLK
Limit Values
1 T
1 T
2 T
2 T
+MCTC+T
+MCTC+T
PCICLK
LBICLK
LBICLK
LBICLK
LBICLK
max.
20
20
20
1 T
+ 20
1 T
+ 20
20
Data Sheet 09.98
PCICLK
PCICLK
)
PEB 20534
1)
LRDY
LRDY
Unit
ns
(ns)
(ns)
ns
ns
(ns)
ns
ns
(ns)
(ns)
(ns)
ns
(ns)
ns
(ns)
ns
ns