PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 62

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
The following table provides an overview of all DMA Controller commands. For detailed
register description refer to Chapter 10.
Table 11
Offset
Addr.
0000
H
Bit-Fields
Pos.
27..24
31..28
21
20
13..10
9
8
0
Access
Type
r/w
DMAC Commands
Controlled
by
CPU
Name
CFGIQ-
SCCiRX
and
CFGIQ-
SCCiTX
and
CFGIQ
CFG,
CFGIQP
TXPRi
IM
IADC
AR
Reset
Value
00000200
Default
0
0
1
0
0
62
H
Register Name
GCMDR:
Global Command Register (page 232)
Description
Configure Interrupt Queue:
These command bits cause the DMAC to
establish or re-configure the dedicated
interrupt queue using the values of the
corresponding base address registers
and interrupt queue length registers.
(only performed if action request bit ’AR’
is set additionally)
Transmit Poll Request Channel i:
If the DMA transmit channel is stopped
on a HOLD
detected), this command forces a read
transaction on the transmit descriptor
verifying the HOLD condition again.
Interrupt Mask:
If
acknowledge interrupt is supressed.
Initialize All DMA Channels:
This bit causes the DMAC to initialize all
transmit and receive channels. The
channel specific commands are ignored
in this case.
Action Request:
This bit causes the DMAC to execute all
commands set in registers GCMDR and
CHiCFG.
set
DMA Controller and Central FIFOs
to
’1’
condition (HOLD bit
the
action
Data Sheet 09.98
PEB 20534
request