PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 31

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 1
Pin No.
197, 199,
201, 202,
205, 4...6,
11...13, 15,
17...20,
37...39, 42,
44, 46...49,
59...64, 66
7, 23, 36, 58 C/BE(3:0) t/s
Semiconductor Group
Symbol
AD(31:0)
PCI Bus Interface(DEMUX Interface)
Input (I)
Output (O)
t/s
Function
Address/Data Bus
A bus transaction consists of an address
phase followed by one or more data phases.
When DSCC4 is Master, AD(31:0) are outputs
in the address phase of a transaction. During
the data phases, AD(31:0) remain outputs for
write transactions, and become inputs for read
transactions.
When DSCC4 is Slave, AD(31:0) are inputs in
the address phase of a transaction. During the
data phases, AD(31:0) remain inputs for write
transactions, and become outputs for read
transactions.
AD(31:0) are updated and sampled on the
rising edge of CLK.
Command/Byte Enable
During the address phase of a transaction,
C/BE(3:0) define the bus command. During
the data phase, C/BE(3:0) are used as Byte
Enables. The Byte Enables are valid for the
entire data phase and determine which byte
lanes carry meaningful data. C/BE0 applies to
byte 0 (lsb) and C/BE3 applies to byte 3 (msb).
When DSCC4 is Master, C/BE(3:0) are
outputs. When DSCC4 is Slave, C/BE(3:0) are
inputs.
C/BE(3:0) are updated and sampled on the
rising edge of CLK.
Note: The bus
31
generated
(target) in DEMUX mode.
command cycle
(initiator)
Pin Descriptions
Data Sheet 09.98
or
PEB 20534
evaluated
is not