PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 264

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Table 58
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit 31
Bit 15
CHiBRDA
30
14
CHiBRDA:
Channel i Base Receive Descriptor Address Register (i=3...0)
i = 3...0
These registers determine the base address of the channel specific
receive descriptor chain and can be located anywhere in the 32 bit
address range.
Note: The descriptor base addresses must be 32-bit aligned, i.e. bit 1
29
13
28
12
and 0 must be set to ’0’.
read/write
0000 000
Channel 0
0054
written by CPU
evaluated by DSCC4
27
11
H
H
26
10
CHiBRDA(15:2)
Channel 1
0060
25
9
CHiBRDA(31:16)
H
24
8
264
23
7
Channel 2
006C
22
6
Detailed Register Description
H
21
5
20
4
Channel 3
0078
19
(RX Channel 3...0)
3
H
Data Sheet 09.98
18
2
PEB 20534
17
1
0
16
0
0