PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 51
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PEB20534H-10
Manufacturer Part Number
PEB20534H-10
Description
DMA Supported Serial Communication Controller with 4 Channels DSCC4
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.PEB20534H-10.pdf
(442 pages)
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4
The DSCC4 may be configured either for 33 MHz/32-bit PCI operation or for a
33 MHz/32-bit De-multiplexed bus interface.
The DSCC4’s DEMUX input pin is used to select the desired configuration:
DEMUX connected to V
The De-multiplexed bus interface mode provides an additional address bus and W/R
control signal extension to the PCI bus interface.
4.1
In this configuration, the DSCC4 interfaces directly to a 33 MHz/32-bit PCI bus. During
run-time, the DSCC4 operates mostly as a PCI Master. However it may also be
accessed by the host processor as a PCI Slave for register read/write or access to
peripherals connected to the LBI.
Device configuration is performed via slave transactions to DSCC4 on-chip registers or
to the PCI Configuration Space.
The DSCC4 is compliant with PCI specification 2.1 at up to 33 MHz.
In addition, the DSCC4 supports little/big endian byte swapping from/to the serial
channels, and unaligned-byte accesses for transmit data sections.
4.1.1
Memory accesses as a PCI Master: The DSCC4 supports both the PCI Memory Write
and PCI Memory Read commands. For the PCI Memory Write command, it writes to an
agent mapped in the memory access space, while for the PCI Read command, it reads
from an agent mapped in the memory address space.
I/O accesses as a PCI Master: The DSCC4 does not support the PCI I/O Write nor PCI
I/O Read commands.
Memory accesses as a PCI Slave: The DSCC4 supports both the PCI Memory Write
and PCI Memory Read commands. For the PCI Memory Write command, the DSCC4 is
written to as an agent mapped in the memory address space, while for the PCI Memory
Read command, the DSCC4 is read from as an agent mapped in the memory address
space.
I/O accesses as a PCI Slave: The DSCC4 does not support the PCI I/O Write nor PCI
I/O Read commands.
Semiconductor Group
connected to V
Microprocessor Bus Interface
PCI Bus Interface
Supported PCI Transactions
SS
DD3
:
:
PCI operation mode
De-multiplexed bus interface mode
51
Microprocessor Bus Interface
Data Sheet 09.98
PEB 20534
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