PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 139

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The columns grouped as ’Control Sources’ cover additional clock mode dependent
control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or
synchronization signals (clock mode 5). The last column describes the function of signal
TxCLK which in some clock modes can be enabled as output signal monitoring the
effective transmit clock or providing a time slot control signal (clock mode 5).
The following is an example of how to read Table 21:
For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate
generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is
derived from the internal oscillator which is supplied by pin XTAL1 and XTAL2.
The REC clock (column ’REC’) is supplied by the internal DPLL which itself is supplied
by the baud rate generator (column ’DPLL’) again.
Note: If one of the clock modes 0b, 4, 6 or 7 is selected the internal oscillator (OSC) is
The first two columns of Table 21 list all possible clock modes configured via bit field
’CM’ and bit ’SSEL’ in register CCR0.
For example, clock mode 6b is choosen by writing a ’6’ to register CCR1.CMi and by
setting bit CCR0.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock
Sources’) specify the source of the internal clocks. Columns REC and TRM correspond
to the domain clock frequencies f
Note: The REC clock is DPLL clock divided by 16.
If enabled by bit ’TOE’ in register CCR2 the resulting transmit clock can be monitored to
pin TxCLK (last column, row ’6b’).
Semiconductor Group
enabled which allows connection of an external crystal to pins XTAL1-XTAL2. The
output signal of the OSC can be used for one serial channel, or for all serial
channels (independent baud rate generators and DPLLs). Moreover, XTAL1
alone can be used as input for an externally generated clock.
REC
and f
Serial Communication Controller (SCC) Cores
139
TRM
.
Data Sheet 09.98
PEB 20534