PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 138

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
The internal structure of each SCC channel consists of 3 clocking domains, transmit,
receive, and system. These three function blocks are clocked with internal transmit
frequency f
(system frequency f
DMA controller). The internal FIFO interfaces are used to transfer data between the
different clock domains.
The clocks f
clock inputs e.g. f
The features of the different clock modes are summarized in table 21.
Table 21
Clock
Mode
CCR0:
CM2,
CM1,CM0
0a
0b
1
2a
2b
3a
3b
4
5
6a
6b
7a
7b
Note: If ASYNC Mode is programmed, some clock mode frequencies can or must be
Configuration
Channel
divided by 16 as selected by the Bit Clock Rate bit CCR1:BCR:
When BCR is set to ‘16’, oversampling (3 samples) in conjunction with majority
decision is performed. BCR has no effect when using clock mode 2, 3a, 4, 5, 6,
or 7a.
CCR0:
SSEL
0
1
X
0
1
0
1
X
X
0
1
0
1
Clock Mode
0a
0b
1
3b, 7b
TRM
TRM
Clock Modes of the SCCs
, internal receive frequency f
to
BRG
–
OSC
–
RxCLK
RxCLK
RxCLK
RxCLK
–
–
OSC
OSC
OSC
OSC
and f
TRM
PCI
and TxCLK input pin.
REC
only supplies the SCC receive and transmit FIFO part facing the
to
DPLL
–
–
–
BRG
BRG
BRG
–
–
–
BRG
BRG
BRG
–
Clock Sources
are internal clocks only and need not be identical to external
to
REC
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
f
f
f
f
f
RxCLK
RxCLK
RxCLK
BRG
REC
Serial Communication Controller (SCC) Cores
to
TRM
TxCLK
BRG
RxCLK
TxCLK
BRG/16
DPLL
BRG
TxCLK
RxCLK
TxCLK
BRG/16
DPLL
BRG
/BCR
/BCR
/BCR
/BCR
138
REC
CD
CD
CD
–
CD
CD
CD
CD
–
–
CD
CD
CD
CD
and system frequency f
R- Strobe
–
–
CD
–
–
–
–
RCG
(TSAR/PC
MMRX)
–
–
–
–
Control Sources
X- Strobe Frame-
–
–
TxCLK
–
–
–
–
TCG
(TSAX/PC
MMTX)
–
–
–
–
f
f
f
f
f
TxCLK
BRG
RxCLK
BRG
TRM
/BCR
/BCR
Sync
–
–
–
–
–
–
–
–
FSC
–
–
–
–
PCI
Data Sheet 09.98
, respectively
PEB 20534
Output
via
TxCLK
(if CCR0:
TOE = ‘1’)
–
BRG
–
–
BRG/16
DPLL
BRG
-
TS-Control
–
BRG/16
DPLL
BRG