PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 237

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 45
CPU Accessibility:
Reset Value:
Ten interrupt queues are provided:
– four queues for receive interrupt vectors of the SCCs (SCCi, i=0...3)
– four queues for transmit interrupt vectors of the SCCs (SCCi, i=0...3)
– one queue for configuration interrupt vectors (action request acknowledge/failed)
– one queue for interrupts of the internal peripherals (SSC, LBI, and GPP).
To clear any bit in the status register, the host CPU must set the corresponding bit to “1“
by register write access. Signal INTA will be deasserted by the DSCC4 if ALL GSTAR
indications are cleared.
Offset Address:
typical usage:
The Global Status Register indicates whether an action request was executed
successfully or not. It also gives information about the interrupt source and which
interrupt queue has been written to when INTA is activated.
Semiconductor Group
Bit 31
Bit 15
SCC
RX
II
3
0
SCC
RX
30
14
II
2
0
GSTAR: Global Status Register
SCC
RX
29
13
II
1
0
SCC
RX
28
12
II
0
0
read/write
0000 000
0004
written by DSCC4 as interrupt indication
evaluated by CPU and written as interrupt confirmation
SCC
27
TX
11
H
II
3
0
Queue Specific Interrupt Indication
SCC
H
26
TX
10
II
2
0
SCC
25
TX
II
1
9
0
SCC
TX
24
8
II
0
0
237
23
7
0
0
22
0
6
0
Action Request Result Status
Detailed Register Description
CFG
21
II
5
0
20
4
0
0
SSC
19
P
3
II
0
Data Sheet 09.98
LBI
18
P
II
2
0
PEB 20534
17
1
0
GPP
16
P
0
II