PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 254

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
Table 52
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit 31
Bit 15
IQPBAR
30
14
IQPBAR:
Interrupt Queue Peripheral Base Address Register
This register determins the base address of the peripheral interrupt
queue and can be located anywhere in the 32 bit address range.
Note: The interrupt queue base address must be 32-bit aligned, i.e. bit 1
29
13
28
12
and 0 must be set to ’0’.
read/write
0000 000
0040
written by CPU
evaluated by DSCC4
27
11
H
H
26
10
IQPBAR(15:2)
25
9
IQPBAR(31:16)
24
8
254
23
7
22
6
Detailed Register Description
21
5
20
4
19
3
Data Sheet 09.98
18
2
PEB 20534
17
1
0
16
0
0
(-)