PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 280

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PEB20534H-10

Manufacturer Part Number
PEB20534H-10
Description
DMA Supported Serial Communication Controller with 4 Channels DSCC4
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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Semiconductor Group
TEC
CEC
FCS
CTS
TIC Executing
TIC=’0’
TIC=’1’
Command Executing
CEC=’0’
CEC=’1’
Note: CEC will be active at most 2.5 receive or transmit clock cycles
Flow Control Status
If (in-band) flow control mechanism is enabled via bit ’FLON’ in register
CCR2 this bit indicates the current state of transmitter:
FCS=’0’
FCS=’1’
Clear To Send Input Signal State
CTS=’0’
CTS=’1’
(depending on whether a receiver or transmitter related command
is executed).
CEC will stay active if the SCC is in power-down mode or if no
serial clock, needed for command execution, is available.
No TIC (transmit immediate character) is currently in
transmission. Access to register TICR is allowed to initiate
a TIC transmission.
A TIC command (write access to register TICR) is
accepted but not completely executed. No further write
access to register TICR is allowed until ’TIC’ bit is cleared
by the DSCC4.
No command is currently in execution. The command
register CMDR can be written by CPU.
A command (written previously to register CMDR) is
currently in execution. No further command can be written
to register CMDR by CPU.
Transmitter is ready (always after transmitter reset
command or XON-character detected).
Transmitter is stopped (XOFF-character detected).
CTS input signal is inactive (high level)
CTS input signal is active (low level)
280
Detailed Register Description
Data Sheet 09.98
(async mode)
(async mode)
PEB 20534
(all modes)
(all modes)

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