ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 19

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
GENERAL DESCRIPTION
The ADuC702x is fully integrated, 1MSPS, 12-bit data
acquisition system incorporating a high performance multi-
channel ADC, a 16/32-bit MCU and Flash/EE Memory on a
single chip.
The ADC consists of up to 12 single-ended inputs. An
additional 4 inputs are available but are multiplexed with the 4
DAC output pins. The 4 DAC outputs are only available on
certain models of the ADuC702x, though in many cases where
the DAC is not present this pin can still be used as an additional
ADC input, giving a maximum of 16 ADC input channels. The
ADC can operate in single-ended or differential input modes.
The ADC input voltage is 0 to V
reference, temperature sensor and voltage comparator complete
the ADC peripheral set.
The ADuC702x also integrates 4 buffered voltage output DACs
on-chip. The DAC output range is programmable to one of
three voltage ranges.
The device operates from an on-chip oscillator and PLL
generating an internal high-frequency clock of 45 MHz. This
clock is routed through a programmable clock divider from
which the MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI, 16/32-bit RISC
machine, offering up to 45 MIPS peak performance. 62k Bytes
of non-volatile Flash/EE are provided on-chip as well as 8k
Bytes of SRAM. The ARM7TDMI core views all memory and
registers as a single linear array.
On-chip factory firmware supports in-circuit serial download
via the UART and JTAG serial interface ports while non-
intrusive emulation is also supported via the JTAG interface.
These features are incorporated into a low-cost QuickStart
Development System supporting this MicroConverter family.
The parts operate from 2.7V to 3.6V and are specified over an
industrial temperature range of -40°C to 125°C. When
operating at 45MHz the power dissipation is 150mW. The
ADuC702x is available in a variety of memory models and
packages. These are detailed on page 9.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8, 16 or 32 bits and the length of the
instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with 4 additional features:
- T support for the Thumb (16 bit) instruction set.
- D support for debug
- M support for long multiplies
- I include the EmbeddedICE module to support embedded
REF
. Low drift bandgap
Rev. PrB | Page 19 of 80
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16-bits, the Thumb instruction set. Faster
execution from 16-bit memory and greater code density can
usually be achieved by using the Thumb instruction set instead
of the ARM instruction set, which makes the ARM7TDMI core
particularly suitable for embedded applications.
However the Thumb mode has two limitations:
- Thumb code usually uses more instructions for the same job,
- The Thumb instruction set does not include some
See ARM7TDMI User Guide for details on the core
architecture, the programming model and both the ARM and
ARM Thumb instruction sets.
Long Multiply (M)
The ARM7TDMI instruction set includes four extra
instructions which perform 32-bit by 32-bit multiplication with
64-bit result and 32-bit by 32-bit multiplication-accumulation
(MAC) with 64-bit result. This result is achieved in a reduced
number of cycles than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers which allow code to be halted for
debugging purposes. These registers are controlled through the
JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be inspected as well as the Flash/EE, the
SRAM and the Memory Mapped Registers.
Exceptions
ARM supports five types of exceptions, and a privileged
processing mode for each type. The five type of exceptions are:
- Normal interrupt or IRQ. It is provided to service general-
- Fast interrupt or FIQ. It is provided to service data transfer or
system debugging.
so ARM code is usually best for maximising the performance
of the time-critical code.
instructions that are needed for exception handling, so the
core will automatically switch to ARM code for exception
handling.
purpose interrupt handling of internal and external events
communication channel with low latency. FIQ has priority
over IRQ
ADuC702x Series