ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 40

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC702x Series
7-6
5
4-3
2
1
0
OSCILLATOR AND PLL - POWER CONTROL
The ADuC702x integrates a 32.768kHz oscillator, a clock
divider and a PLL. The PLL locks onto a multiple (1376) of the
internal oscillator to provide a stable 45MHz clock for the
system. The core can operate at this frequency, or at binary
submultiples of it, to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.6 MHz. The core
clock frequency can be output on the ECLK pin as described
Figure 20. A power down mode is available on the ADuC702x.
The operating mode, clocking mode and programmable clock
divider are controlled via two MMRs, PLLCON and POWCON.
PLLCON controls operating mode of the clock system while
POWCON controls the core clock frequency and the power-
down mode.
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
10
11
Comparator output configuration bits:
00
01
10
11
Comparator output logic state bit
When low the comparator output is high when the positive input (CMP0) is above the negative input
(CMP1).
When high, the comparator output is high when the positive input is below the negative input
Response time
00
01
10
11
Comparator hysteresis bit:
Set by user to have an hysteresis of about 7.5mV
Cleared by user to have no hysteresis
Comparator output rising edge interrupt
Set automatically when a rising edge occurs on the monitored voltage (CMP0)
Cleared by user by writing a 1 to this bit.
Comparator output falling edge interrupt
Set automatically when a falling edge occurs on the monitored voltage (CMP0)
Cleared by user
DAC0
Start ADC conversion
Reserved
Reserved
Output on CMP
IRQ
10µs
5µs
1µs
0.5µs
OUT
Rev. PrB | Page 40 of 80
A certain sequence has to be followed to write in the PLLCON
and POWCON registers, to prevent accidental programming.
PLLCON:
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
* 32.768kHz +/-3%
WATCHDOG
WAKEUP
TIMER
TIMER
SCLKS
Preliminary Technical Data
32.768kHz
Figure 20: clocking system
OSCILLATOR
INT. 32kHz *
CORE
PLL
CD
45MHz
POWCON:
POWKEY1 = 0x01
POWCON = 0x00
POWKEY1 = 0xF4
P0.7/ECLK
AT
POWER
UP
/2
OSCILLATOR
CD
CRYSTAL
MDCLK
MDCLK
PERIPHERALS
ANALOG
XCLKO
XCLKI
XCLK