ADUC702 AD [Analog Devices], ADUC702 Datasheet - Page 45

• Manufacturer Part Number: ADUC702
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
symmetrical output patterns.
Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA
register that indicates whether operation is in the first or
second half cycle of the PWM period.
The resultant on-times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as:
And the corresponding duty cycles:
The minimum permissible T
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is T
The output signals from the timing unit for operation in double
update mode are shown in Figure 23. This illustrates a
completely general case where the switching frequency, dead
time and duty cycle are all changed in the second half of the
PWM period. Of course, the same value for any or all of these
quantities could be used in both halves of the PWM cycle.
However, it can be seen that there is no guarantee that
symmetrical PWM signals will be produced by the timing unit
in double update mode. Additionally, it is seen that the dead
time is inserted into the PWM signals in the same way as in the
single update mode.
PWMSTA (0)
In general the on-times of the PWM signals in double update
mode can be defined as:
T
d
PWMSYNC
T
0H
Figure 23: Typical PWM outputs of the Three-phase timing unit in double
d
0L
0L
0H
= (PWMCH0
= T
= 2 x (PWMDAT0 – PWMCH0 – PWMDAT1) x t
= T
0H
0L
0L
0H
T
/ Ts = (PWMDAT0 – PWMCH0 – PWMDAT1)
0H
/ Ts = (
= 2 x (PWMCH0 - PWMDAT1) x t
2 x
PWMDAT1 1
PWMDAT0 1
1
+ PWMCH0
PWMCH0 – PWMDAT1) /
S
PWMDAT2 1 +1
, corresponding to a 100% duty cycle.
PWMCH0 1
PWMDAT0
update mode
x t
CORE
2
0H
– PWMDAT1
and T
PWMCH0 2
PWMDAT0 2
0L
PWMDAT2 2 +1
values are zero,
1
PWMDAT1 2
– PWMDAT1
PWMDAT0
CORE
2 x
CORE
Rev. PrB | Page 45 of 80
/
2
)
T
PWMDAT1
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
d
PWMDAT1
d
PWMCH0
PWMDAT0
since for the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 22 and
Figure 23 can be produced on the 1H, 1L, 2H and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a
manner identical to that described for PWMCH0. The PWM
controller does not produce any PWM outputs until all of the
PWMDAT0, PWMCH0, PWMCH1 and PWMCH2 registers
have been written to at least once. Once these registers have
been written, internal counting of the timers in the three-phase
timing unit is enabled. Writing to the PWMDAT0 register
starts the internal timing of the main PWM timer. Provided the
PWMDAT0 register is written prior to the PWMCH0,
PWMCH1 and PWMCH2 registers in the initialisation, the
first PWMSYNC pulse and interrupt (if enabled) appear 1.5 x
t
PWMDAT0 register in single update mode. In double update
mode, the first PWMSYNC pulse appears after PWMDAT0 x
t
Output Control Unit
The operation of the Output Control Unit is controlled by the
9-bit read/write PWMEN register. This register controls two
distinct features of the Output Control Unit that are directly
useful in the control of ECM or BDCM. The PWMEN register
contains three crossover bits, one for each pair of PWM outputs.
Setting Bit 8 of the PWMEN register enables the crossover
mode for the 0H/0L pair of PWM signals, setting Bit 7 enables
crossover on the 1H/1L pair of PWM signals and setting Bit 6
enables crossover on the 2H/2L pair of PWM signals. If
crossover mode is enabled for any pair of PWM signals, the
high-side PWM signal from the timing unit (0H, for example) is
diverted to the associated low-side output of the Output
Control Unit so that the signal will ultimately appear at the 0L
pin. Of course, the corresponding low-side output of the Timing
Unit is also diverted to the complementary high-side output of
CORE
CORE
0H
0L
0L
= (PWMDAT0
= T
= T
seconds.
x PWMDAT0 seconds after the initial write to the
0H
0L
/ Ts = (PWMCH0
/Ts = (PWMDAT0
S
2
Ts =
.
1
2
2
– PWMDAT1
) / (PWMDAT0
)
– PWMDAT1
(PWMDAT0
1
+ PWMDAT0
0H
and T
1
2
1
) x t
1
+ PWMCH0
– PWMDAT1
1
+ PWMDAT0
1
+ PWMDAT0
0L
CORE
+ PWMDAT0
are constrained to lie between
2
ADuC702x Series
- PWMCH0
2
– PWMDAT1
2
2
) / (PWMDAT0
2
)
) x t
2
1
- PWMCH0
- PWMCH0
CORE
1
–
1
1
2
+
–
-